
prime-number-c:     file format elf64-littleaarch64


Disassembly of section .init:

0000000000400608 <_init>:
  400608:	a9bf7bfd 	stp	x29, x30, [sp, #-16]!
  40060c:	910003fd 	mov	x29, sp
  400610:	94000042 	bl	400718 <call_weak_fn>
  400614:	a8c17bfd 	ldp	x29, x30, [sp], #16
  400618:	d65f03c0 	ret

Disassembly of section .plt:

0000000000400620 <.plt>:
  400620:	a9bf7bf0 	stp	x16, x30, [sp, #-16]!
  400624:	90000090 	adrp	x16, 410000 <__FRAME_END__+0xf438>
  400628:	f947fe11 	ldr	x17, [x16, #4088]
  40062c:	913fe210 	add	x16, x16, #0xff8
  400630:	d61f0220 	br	x17
  400634:	d503201f 	nop
  400638:	d503201f 	nop
  40063c:	d503201f 	nop

0000000000400640 <puts@plt>:
  400640:	b0000090 	adrp	x16, 411000 <puts@GLIBC_2.17>
  400644:	f9400211 	ldr	x17, [x16]
  400648:	91000210 	add	x16, x16, #0x0
  40064c:	d61f0220 	br	x17

0000000000400650 <free@plt>:
  400650:	b0000090 	adrp	x16, 411000 <puts@GLIBC_2.17>
  400654:	f9400611 	ldr	x17, [x16, #8]
  400658:	91002210 	add	x16, x16, #0x8
  40065c:	d61f0220 	br	x17

0000000000400660 <memset@plt>:
  400660:	b0000090 	adrp	x16, 411000 <puts@GLIBC_2.17>
  400664:	f9400a11 	ldr	x17, [x16, #16]
  400668:	91004210 	add	x16, x16, #0x10
  40066c:	d61f0220 	br	x17

0000000000400670 <__libc_start_main@plt>:
  400670:	b0000090 	adrp	x16, 411000 <puts@GLIBC_2.17>
  400674:	f9400e11 	ldr	x17, [x16, #24]
  400678:	91006210 	add	x16, x16, #0x18
  40067c:	d61f0220 	br	x17

0000000000400680 <clock@plt>:
  400680:	b0000090 	adrp	x16, 411000 <puts@GLIBC_2.17>
  400684:	f9401211 	ldr	x17, [x16, #32]
  400688:	91008210 	add	x16, x16, #0x20
  40068c:	d61f0220 	br	x17

0000000000400690 <malloc@plt>:
  400690:	b0000090 	adrp	x16, 411000 <puts@GLIBC_2.17>
  400694:	f9401611 	ldr	x17, [x16, #40]
  400698:	9100a210 	add	x16, x16, #0x28
  40069c:	d61f0220 	br	x17

00000000004006a0 <abort@plt>:
  4006a0:	b0000090 	adrp	x16, 411000 <puts@GLIBC_2.17>
  4006a4:	f9401a11 	ldr	x17, [x16, #48]
  4006a8:	9100c210 	add	x16, x16, #0x30
  4006ac:	d61f0220 	br	x17

00000000004006b0 <__gmon_start__@plt>:
  4006b0:	b0000090 	adrp	x16, 411000 <puts@GLIBC_2.17>
  4006b4:	f9401e11 	ldr	x17, [x16, #56]
  4006b8:	9100e210 	add	x16, x16, #0x38
  4006bc:	d61f0220 	br	x17

00000000004006c0 <printf@plt>:
  4006c0:	b0000090 	adrp	x16, 411000 <puts@GLIBC_2.17>
  4006c4:	f9402211 	ldr	x17, [x16, #64]
  4006c8:	91010210 	add	x16, x16, #0x40
  4006cc:	d61f0220 	br	x17

Disassembly of section .text:

00000000004006d0 <_start>:
  4006d0:	d280001d 	mov	x29, #0x0                   	// #0
  4006d4:	d280001e 	mov	x30, #0x0                   	// #0
  4006d8:	aa0003e5 	mov	x5, x0
  4006dc:	f94003e1 	ldr	x1, [sp]
  4006e0:	910023e2 	add	x2, sp, #0x8
  4006e4:	910003e6 	mov	x6, sp
  4006e8:	580000c0 	ldr	x0, 400700 <_start+0x30>
  4006ec:	580000e3 	ldr	x3, 400708 <_start+0x38>
  4006f0:	58000104 	ldr	x4, 400710 <_start+0x40>
  4006f4:	97ffffdf 	bl	400670 <__libc_start_main@plt>
  4006f8:	97ffffea 	bl	4006a0 <abort@plt>
  4006fc:	00000000 	.inst	0x00000000 ; undefined
  400700:	00400950 	.word	0x00400950
  400704:	00000000 	.word	0x00000000
  400708:	00400a60 	.word	0x00400a60
  40070c:	00000000 	.word	0x00000000
  400710:	00400ae0 	.word	0x00400ae0
  400714:	00000000 	.word	0x00000000

0000000000400718 <call_weak_fn>:
  400718:	90000080 	adrp	x0, 410000 <__FRAME_END__+0xf438>
  40071c:	f947f000 	ldr	x0, [x0, #4064]
  400720:	b4000040 	cbz	x0, 400728 <call_weak_fn+0x10>
  400724:	17ffffe3 	b	4006b0 <__gmon_start__@plt>
  400728:	d65f03c0 	ret
  40072c:	00000000 	.inst	0x00000000 ; undefined

0000000000400730 <deregister_tm_clones>:
  400730:	b0000080 	adrp	x0, 411000 <puts@GLIBC_2.17>
  400734:	91016000 	add	x0, x0, #0x58
  400738:	b0000081 	adrp	x1, 411000 <puts@GLIBC_2.17>
  40073c:	91016021 	add	x1, x1, #0x58
  400740:	eb00003f 	cmp	x1, x0
  400744:	540000a0 	b.eq	400758 <deregister_tm_clones+0x28>  // b.none
  400748:	90000001 	adrp	x1, 400000 <_init-0x608>
  40074c:	f9458021 	ldr	x1, [x1, #2816]
  400750:	b4000041 	cbz	x1, 400758 <deregister_tm_clones+0x28>
  400754:	d61f0020 	br	x1
  400758:	d65f03c0 	ret
  40075c:	d503201f 	nop

0000000000400760 <register_tm_clones>:
  400760:	b0000080 	adrp	x0, 411000 <puts@GLIBC_2.17>
  400764:	91016000 	add	x0, x0, #0x58
  400768:	b0000081 	adrp	x1, 411000 <puts@GLIBC_2.17>
  40076c:	91016021 	add	x1, x1, #0x58
  400770:	cb000021 	sub	x1, x1, x0
  400774:	9343fc21 	asr	x1, x1, #3
  400778:	8b41fc21 	add	x1, x1, x1, lsr #63
  40077c:	9341fc21 	asr	x1, x1, #1
  400780:	b40000a1 	cbz	x1, 400794 <register_tm_clones+0x34>
  400784:	90000002 	adrp	x2, 400000 <_init-0x608>
  400788:	f9458442 	ldr	x2, [x2, #2824]
  40078c:	b4000042 	cbz	x2, 400794 <register_tm_clones+0x34>
  400790:	d61f0040 	br	x2
  400794:	d65f03c0 	ret

0000000000400798 <__do_global_dtors_aux>:
  400798:	a9be7bfd 	stp	x29, x30, [sp, #-32]!
  40079c:	910003fd 	mov	x29, sp
  4007a0:	f9000bf3 	str	x19, [sp, #16]
  4007a4:	b0000093 	adrp	x19, 411000 <puts@GLIBC_2.17>
  4007a8:	39416260 	ldrb	w0, [x19, #88]
  4007ac:	35000080 	cbnz	w0, 4007bc <__do_global_dtors_aux+0x24>
  4007b0:	97ffffe0 	bl	400730 <deregister_tm_clones>
  4007b4:	52800020 	mov	w0, #0x1                   	// #1
  4007b8:	39016260 	strb	w0, [x19, #88]
  4007bc:	f9400bf3 	ldr	x19, [sp, #16]
  4007c0:	a8c27bfd 	ldp	x29, x30, [sp], #32
  4007c4:	d65f03c0 	ret

00000000004007c8 <frame_dummy>:
  4007c8:	17ffffe6 	b	400760 <register_tm_clones>

00000000004007cc <_Z5countj>:
  4007cc:	d10083ff 	sub	sp, sp, #0x20
  4007d0:	b9000fe0 	str	w0, [sp, #12]
  4007d4:	b9001fff 	str	wzr, [sp, #28]
  4007d8:	b9400fe0 	ldr	w0, [sp, #12]
  4007dc:	b9001be0 	str	w0, [sp, #24]
  4007e0:	b9401be0 	ldr	w0, [sp, #24]
  4007e4:	7100001f 	cmp	w0, #0x0
  4007e8:	54000180 	b.eq	400818 <_Z5countj+0x4c>  // b.none
  4007ec:	b9401be0 	ldr	w0, [sp, #24]
  4007f0:	12000000 	and	w0, w0, #0x1
  4007f4:	7100001f 	cmp	w0, #0x0
  4007f8:	54000080 	b.eq	400808 <_Z5countj+0x3c>  // b.none
  4007fc:	b9401fe0 	ldr	w0, [sp, #28]
  400800:	11000400 	add	w0, w0, #0x1
  400804:	b9001fe0 	str	w0, [sp, #28]
  400808:	b9401be0 	ldr	w0, [sp, #24]
  40080c:	53017c00 	lsr	w0, w0, #1
  400810:	b9001be0 	str	w0, [sp, #24]
  400814:	17fffff3 	b	4007e0 <_Z5countj+0x14>
  400818:	b9401fe0 	ldr	w0, [sp, #28]
  40081c:	910083ff 	add	sp, sp, #0x20
  400820:	d65f03c0 	ret

0000000000400824 <_Z5sievePj>:
  400824:	d10083ff 	sub	sp, sp, #0x20
  400828:	f90007e0 	str	x0, [sp, #8]
  40082c:	52800040 	mov	w0, #0x2                   	// #2
  400830:	b9001fe0 	str	w0, [sp, #28]
  400834:	b9401fe1 	ldr	w1, [sp, #28]
  400838:	5284e200 	mov	w0, #0x2710                	// #10000
  40083c:	6b00003f 	cmp	w1, w0
  400840:	5400082c 	b.gt	400944 <_Z5sievePj+0x120>
  400844:	b9401fe0 	ldr	w0, [sp, #28]
  400848:	11007c01 	add	w1, w0, #0x1f
  40084c:	7100001f 	cmp	w0, #0x0
  400850:	1a80b020 	csel	w0, w1, w0, lt  // lt = tstop
  400854:	13057c00 	asr	w0, w0, #5
  400858:	93407c00 	sxtw	x0, w0
  40085c:	d37ef400 	lsl	x0, x0, #2
  400860:	f94007e1 	ldr	x1, [sp, #8]
  400864:	8b000020 	add	x0, x1, x0
  400868:	b9400001 	ldr	w1, [x0]
  40086c:	b9401fe0 	ldr	w0, [sp, #28]
  400870:	6b0003e2 	negs	w2, w0
  400874:	12001000 	and	w0, w0, #0x1f
  400878:	12001042 	and	w2, w2, #0x1f
  40087c:	5a824400 	csneg	w0, w0, w2, mi  // mi = first
  400880:	52800022 	mov	w2, #0x1                   	// #1
  400884:	1ac02040 	lsl	w0, w2, w0
  400888:	0a000020 	and	w0, w1, w0
  40088c:	7100001f 	cmp	w0, #0x0
  400890:	54000520 	b.eq	400934 <_Z5sievePj+0x110>  // b.none
  400894:	b9401fe1 	ldr	w1, [sp, #28]
  400898:	b9401fe0 	ldr	w0, [sp, #28]
  40089c:	1b007c20 	mul	w0, w1, w0
  4008a0:	b9001be0 	str	w0, [sp, #24]
  4008a4:	b9401be1 	ldr	w1, [sp, #24]
  4008a8:	529c1fe0 	mov	w0, #0xe0ff                	// #57599
  4008ac:	72a0bea0 	movk	w0, #0x5f5, lsl #16
  4008b0:	6b00003f 	cmp	w1, w0
  4008b4:	5400040c 	b.gt	400934 <_Z5sievePj+0x110>
  4008b8:	b9401be0 	ldr	w0, [sp, #24]
  4008bc:	11007c01 	add	w1, w0, #0x1f
  4008c0:	7100001f 	cmp	w0, #0x0
  4008c4:	1a80b020 	csel	w0, w1, w0, lt  // lt = tstop
  4008c8:	13057c00 	asr	w0, w0, #5
  4008cc:	2a0003e4 	mov	w4, w0
  4008d0:	93407c80 	sxtw	x0, w4
  4008d4:	d37ef400 	lsl	x0, x0, #2
  4008d8:	f94007e1 	ldr	x1, [sp, #8]
  4008dc:	8b000020 	add	x0, x1, x0
  4008e0:	b9400001 	ldr	w1, [x0]
  4008e4:	b9401be0 	ldr	w0, [sp, #24]
  4008e8:	6b0003e2 	negs	w2, w0
  4008ec:	12001000 	and	w0, w0, #0x1f
  4008f0:	12001042 	and	w2, w2, #0x1f
  4008f4:	5a824400 	csneg	w0, w0, w2, mi  // mi = first
  4008f8:	52800022 	mov	w2, #0x1                   	// #1
  4008fc:	1ac02040 	lsl	w0, w2, w0
  400900:	2a2003e0 	mvn	w0, w0
  400904:	2a0003e3 	mov	w3, w0
  400908:	93407c80 	sxtw	x0, w4
  40090c:	d37ef400 	lsl	x0, x0, #2
  400910:	f94007e2 	ldr	x2, [sp, #8]
  400914:	8b000040 	add	x0, x2, x0
  400918:	0a030021 	and	w1, w1, w3
  40091c:	b9000001 	str	w1, [x0]
  400920:	b9401be1 	ldr	w1, [sp, #24]
  400924:	b9401fe0 	ldr	w0, [sp, #28]
  400928:	0b000020 	add	w0, w1, w0
  40092c:	b9001be0 	str	w0, [sp, #24]
  400930:	17ffffdd 	b	4008a4 <_Z5sievePj+0x80>
  400934:	b9401fe0 	ldr	w0, [sp, #28]
  400938:	11000400 	add	w0, w0, #0x1
  40093c:	b9001fe0 	str	w0, [sp, #28]
  400940:	17ffffbd 	b	400834 <_Z5sievePj+0x10>
  400944:	d503201f 	nop
  400948:	910083ff 	add	sp, sp, #0x20
  40094c:	d65f03c0 	ret

0000000000400950 <main>:
  400950:	a9bd7bfd 	stp	x29, x30, [sp, #-48]!
  400954:	910003fd 	mov	x29, sp
  400958:	97ffff4a 	bl	400680 <clock@plt>
  40095c:	f90013a0 	str	x0, [x29, #32]
  400960:	d2978400 	mov	x0, #0xbc20                	// #48160
  400964:	f2a017c0 	movk	x0, #0xbe, lsl #16
  400968:	97ffff4a 	bl	400690 <malloc@plt>
  40096c:	f9000fa0 	str	x0, [x29, #24]
  400970:	f9400fa0 	ldr	x0, [x29, #24]
  400974:	f100001f 	cmp	x0, #0x0
  400978:	540000c1 	b.ne	400990 <main+0x40>  // b.any
  40097c:	90000000 	adrp	x0, 400000 <_init-0x608>
  400980:	912c4000 	add	x0, x0, #0xb10
  400984:	97ffff2f 	bl	400640 <puts@plt>
  400988:	12800000 	mov	w0, #0xffffffff            	// #-1
  40098c:	14000032 	b	400a54 <main+0x104>
  400990:	d2978402 	mov	x2, #0xbc20                	// #48160
  400994:	f2a017c2 	movk	x2, #0xbe, lsl #16
  400998:	52801fe1 	mov	w1, #0xff                  	// #255
  40099c:	f9400fa0 	ldr	x0, [x29, #24]
  4009a0:	97ffff30 	bl	400660 <memset@plt>
  4009a4:	f9400fa0 	ldr	x0, [x29, #24]
  4009a8:	97ffff9f 	bl	400824 <_Z5sievePj>
  4009ac:	12800020 	mov	w0, #0xfffffffe            	// #-2
  4009b0:	b9002ba0 	str	w0, [x29, #40]
  4009b4:	b9002fbf 	str	wzr, [x29, #44]
  4009b8:	b9402fa1 	ldr	w1, [x29, #44]
  4009bc:	5295e0e0 	mov	w0, #0xaf07                	// #44807
  4009c0:	72a005e0 	movk	w0, #0x2f, lsl #16
  4009c4:	6b00003f 	cmp	w1, w0
  4009c8:	540001ec 	b.gt	400a04 <main+0xb4>
  4009cc:	b9802fa0 	ldrsw	x0, [x29, #44]
  4009d0:	d37ef400 	lsl	x0, x0, #2
  4009d4:	f9400fa1 	ldr	x1, [x29, #24]
  4009d8:	8b000020 	add	x0, x1, x0
  4009dc:	b9400000 	ldr	w0, [x0]
  4009e0:	97ffff7b 	bl	4007cc <_Z5countj>
  4009e4:	2a0003e1 	mov	w1, w0
  4009e8:	b9402ba0 	ldr	w0, [x29, #40]
  4009ec:	0b010000 	add	w0, w0, w1
  4009f0:	b9002ba0 	str	w0, [x29, #40]
  4009f4:	b9402fa0 	ldr	w0, [x29, #44]
  4009f8:	11000400 	add	w0, w0, #0x1
  4009fc:	b9002fa0 	str	w0, [x29, #44]
  400a00:	17ffffee 	b	4009b8 <main+0x68>
  400a04:	f9400fa0 	ldr	x0, [x29, #24]
  400a08:	97ffff12 	bl	400650 <free@plt>
  400a0c:	97ffff1d 	bl	400680 <clock@plt>
  400a10:	aa0003e1 	mov	x1, x0
  400a14:	f94013a0 	ldr	x0, [x29, #32]
  400a18:	cb000020 	sub	x0, x1, x0
  400a1c:	d29ef9e1 	mov	x1, #0xf7cf                	// #63439
  400a20:	f2bc6a61 	movk	x1, #0xe353, lsl #16
  400a24:	f2d374a1 	movk	x1, #0x9ba5, lsl #32
  400a28:	f2e41881 	movk	x1, #0x20c4, lsl #48
  400a2c:	9b417c01 	smulh	x1, x0, x1
  400a30:	9347fc21 	asr	x1, x1, #7
  400a34:	937ffc00 	asr	x0, x0, #63
  400a38:	cb000020 	sub	x0, x1, x0
  400a3c:	9e620000 	scvtf	d0, x0
  400a40:	90000000 	adrp	x0, 400000 <_init-0x608>
  400a44:	912ca000 	add	x0, x0, #0xb28
  400a48:	b9402ba1 	ldr	w1, [x29, #40]
  400a4c:	97ffff1d 	bl	4006c0 <printf@plt>
  400a50:	52800000 	mov	w0, #0x0                   	// #0
  400a54:	a8c37bfd 	ldp	x29, x30, [sp], #48
  400a58:	d65f03c0 	ret
  400a5c:	00000000 	.inst	0x00000000 ; undefined

0000000000400a60 <__libc_csu_init>:
  400a60:	a9bc7bfd 	stp	x29, x30, [sp, #-64]!
  400a64:	910003fd 	mov	x29, sp
  400a68:	a901d7f4 	stp	x20, x21, [sp, #24]
  400a6c:	90000094 	adrp	x20, 410000 <__FRAME_END__+0xf438>
  400a70:	90000095 	adrp	x21, 410000 <__FRAME_END__+0xf438>
  400a74:	9136c294 	add	x20, x20, #0xdb0
  400a78:	9136a2b5 	add	x21, x21, #0xda8
  400a7c:	a902dff6 	stp	x22, x23, [sp, #40]
  400a80:	cb150294 	sub	x20, x20, x21
  400a84:	f9001ff8 	str	x24, [sp, #56]
  400a88:	2a0003f6 	mov	w22, w0
  400a8c:	aa0103f7 	mov	x23, x1
  400a90:	9343fe94 	asr	x20, x20, #3
  400a94:	aa0203f8 	mov	x24, x2
  400a98:	97fffedc 	bl	400608 <_init>
  400a9c:	b4000194 	cbz	x20, 400acc <__libc_csu_init+0x6c>
  400aa0:	f9000bb3 	str	x19, [x29, #16]
  400aa4:	d2800013 	mov	x19, #0x0                   	// #0
  400aa8:	f8737aa3 	ldr	x3, [x21, x19, lsl #3]
  400aac:	aa1803e2 	mov	x2, x24
  400ab0:	aa1703e1 	mov	x1, x23
  400ab4:	2a1603e0 	mov	w0, w22
  400ab8:	91000673 	add	x19, x19, #0x1
  400abc:	d63f0060 	blr	x3
  400ac0:	eb13029f 	cmp	x20, x19
  400ac4:	54ffff21 	b.ne	400aa8 <__libc_csu_init+0x48>  // b.any
  400ac8:	f9400bb3 	ldr	x19, [x29, #16]
  400acc:	a941d7f4 	ldp	x20, x21, [sp, #24]
  400ad0:	a942dff6 	ldp	x22, x23, [sp, #40]
  400ad4:	f9401ff8 	ldr	x24, [sp, #56]
  400ad8:	a8c47bfd 	ldp	x29, x30, [sp], #64
  400adc:	d65f03c0 	ret

0000000000400ae0 <__libc_csu_fini>:
  400ae0:	d65f03c0 	ret

Disassembly of section .fini:

0000000000400ae4 <_fini>:
  400ae4:	a9bf7bfd 	stp	x29, x30, [sp, #-16]!
  400ae8:	910003fd 	mov	x29, sp
  400aec:	a8c17bfd 	ldp	x29, x30, [sp], #16
  400af0:	d65f03c0 	ret
